Memory devices have seen explosive growth with the advancement of electronic applications, such as memory cards, portable electronic devices, cell phones, MP3 players, digital and video cameras, and other consumer electronics. Application requirements for low cost, power consumption and high performance are driving memory design to different architectures. Floating gate structures continue to dominate non-volatile memory technology. These structures typically use polysilicon floating gates as the storage node and are arranged in various memory arrays to achieve architectures such as NAND flash and NOR flash memory. To program and erase the memory cell, electron tunneling methods are used to place or remove electrons from the floating gate.
FIG. 1 shows a prior art flash memory structure 100 having a 1-bit memory cell. The memory structure 100 includes a P-type substrate 102 having N+ dopant diffused areas 103. A tunnel oxide layer 104 is formed on P-type substrate 102 above the N+ dopant areas that function as a drain and source 103A and 103B, respectively. A first polysilicon layer 105 is formed on the tunnel oxide layer 104 that functions as a floating gate (floating gate 105). A dielectric layer 106 is formed on the floating gate layer 105 with a second polysilicon layer 107 formed on the dielectric layer 106 that functions as a control gate (control gate 107). Depending on the voltage applied to the control gate 107, electron tunneling through the tunnel oxide layer 104 will place or remove electrons in the floating gate 105 to store 1-bit of data. This type of prior memory structure only stores 1-bit of data per memory cell. Because of increased density requirements in consumer electronics, there is a need for memory devices to have more than 1-bit of data per memory cell.